Intern
RESPONSIBILITES:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.
2. Work with Front-end designers to optimizetiming/area/power of the design implementation and perform static timinganalysis.
3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).
4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
Requirements:
1.CS/EE or background in areas related todigital or analog chip design
2.Known of IC backend flow.
3.Known of timing concept.
4.Have reading and writing skills forenglish
5.Experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.
6.Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
7.Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
8.Experience and knowledge about FE design(RTL code, flow) and verification is a plus.
9.Good analytical and debugging skills.
New Graduates
RESPONSIBILITES:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.
2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.
3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).
4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
Requirements:
1.CS/EE or background in areas related todigital or analog chip design
2.Be familiar with IC backend flow.
3.Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
4.Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
5.Experience and knowledge about FE design(RTL code, flow) and verification is a plus.
6.Good analytical and debugging skills.
Senior Engineer
RESPONSIBILITES:
1. Responsible for developing digital designswith emphasis on backend, including Floor-plan, power planning, Place, CTS andRoute.
2. Work with Front-end designers to optimize timing/area/powerof the design implementation and perform static timing analysis.
3. Optimization and Verification of layoutfor tape-out (including RC extraction, ECO, DRC, LVS).
4. Static Timing analysis (Prime Time or ETS)and setup/hold fix.
Requirements:
1.CS/EE or background in areas related todigital or analog chip design
2.3 year+ work experience.
3.experience in floorplan, place, cts,route, timing ,pv and power analysis and so on.
4.Experienced in Synopsys/Cadenceautomatically physical implementation tools and flows (IC-Compiler/ Astro /SOC-Encounter/ Milky-way/ Star-RCX) is a plus.
5.Experience with one or more scriptinglanguages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.
6.Experience and knowledge about FE design(RTL code, flow) and verification is a plus.
7.Good analytical and debugging skills.
Send your CV to hr@magic-semi.com if you are interested.